Stacked semiconductor device and method of producing the same

ABSTRACT

In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is a division of Ser. No. 09/940,625, filed Aug.29, 2001.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention generally relates to semiconductor devicesand methods of producing the semiconductor devices, and, moreparticularly, to a stacked semiconductor device having a plurality ofsemiconductor chips stacked as one package and a method of producingsuch a stacked semiconductor device.

[0004] 2. Description of the Related Art

[0005] In recent years, portable electronic devices such as mobiletelephones and non-volatile memory media such as IC memory cards havebeen becoming smaller and smaller. Along with this trend, there havebeen demands for devices and memory media having a smaller number ofcomponents and a smaller size. Accordingly, it is desired to develop atechnique of effectively packaging semiconductor chips that are maincomponents constituting those electronic devices and memory media.Examples of such packages that satisfy the above demands include a chipscale package (CSP) that is almost as small as a semiconductor chip anda multi-chip package (MCP) that accommodates a plurality ofsemiconductor chips in one package.

[0006] The CSP or MCP is realized by stacking and turning a plurality ofsemiconductor chips into one package. This technique is represented by astacked multi-chip package (SMCP).

[0007]FIG. 1 shows the structure of a conventional S-MCP in which twosemiconductor chips are stacked. As shown in FIG. 1, a semiconductorchip 2 is mounted on a substrate 4, another semiconductor chip 6 that issmaller than the semiconductor chip 2 is stacked on the semiconductorchip 2. Electrodes of the semiconductor chips 2 and 6 are connected tothe pads of a substrate 4 by bonding wires 8, and the pads of thesubstrate 4 are electrically connected to external connecting terminals10. The semiconductor chips 2 and 6, and the bonding wires 8 areencapsulated by an encapsulation-resin 12.

[0008] A stacked CSP has a stacked structure to that of the S-MCP shownin FIG. 1.

[0009] In the above conventional S-MCP, however, the upper semiconductorchip 6 must be smaller than the lower semiconductor chip 2. The uppersemiconductor chip 6 needs to be small enough not to cover theelectrodes of the lower semiconductor chip 2. On the other hand, if theupper semiconductor chip 6 is much too smaller than the lowersemiconductor chip 2, the distance between the electrodes of the uppersemiconductor chip 6 and the pads of the substrate 4 becomes too long toperform a proper wire bonding operation.

[0010]FIGS. 2A to 2D show the positional relationship between the uppersemiconductor chip and the lower semiconductor chip.

[0011]FIG. 2A shows the positional relationship between two properlystacked semiconductor chips. More specifically, the upper semiconductorchip 6 is small enough not to cover the electrodes of the lowersemiconductor chip 2, and the electrodes of the upper semiconductor chip6 and the electrodes of the lower semiconductor chip 2 can be connectedto the pads of the substrate 4 by bonding wires

[0012]FIG. 2B shows semiconductor chips that cannot be stacked. Morespecifically, the upper semiconductor chip 6 is almost as large as thelower semiconductor chip 2 in FIG. 2B. If the upper semiconductor chip 6is stacked on the lower semiconductor chip 2, the upper semiconductorchip 6 will cover the electrodes of the lower semiconductor chip 2,resulting in a failure in the wire bonding of the electrodes of thelower semiconductor chip 2.

[0013]FIG. 2C shows an example in which the two semiconductor chips canbe stacked, but there is a problem with the wire bonding. Morespecifically, since the upper semiconductor chip 6 is much smaller thanthe lower semiconductor chip 2 in FIG. 2C, the distance between theelectrodes of the upper semiconductor chip 6 and the pads of thesubstrate 4 becomes too long to perform a proper wire bonding process.Even if the wire bonding is successful, the bonding wires 8 are so longthat it needs to be bent. In such a case, the bent portion might touchother components in the surrounding area, resulting in other problems.

[0014]FIG. 2D shows an example in which the two semiconductor chips canbe stacked, but the package size becomes too large. More specifically,in FIG. 2D, the upper semiconductor chip 6 can be stacked on the lowersemiconductor chip 2, without covering the electrodes of lowersemiconductor chip 2. However, the upper semiconductor chip 6 is toolarge in width, resulting in sticking out from the lower semiconductorchip 2 to a great extent. In this structure, the package cannot be madesmaller in size. Also, since the sticking out portions of the uppersemiconductor chip are not supported from below, the upper semiconductorchip 6 might be damaged by a pressing force caused by the capillary of awire bonder pressed against the electrodes of the upper semiconductorchip 6.

[0015] As described above, in the conventional S-MCP, semiconductorchips of the same size (i.e., of the same type) cannot be stacked. Asthe sizes of the semiconductor chips that can be stacked are limited,the types of the semiconductor chips that can be employed in the S-MCPare also limited.

[0016] Examples of the method of stacking semiconductor chips of thesame type include a method of bonding two reverse semiconductor chips.In this method, the reverse sides of both reverse semiconductor chipsare bonded to each other, so that the electrodes are symmetricallyarranged. However, two different types of masks are required in theproduction process of such reverse semiconductor chips, resulting inhigh production costs.

[0017] In a case of rectangular semiconductor chips, the semiconductorchips of the same type can be rotated by 90 degrees with each other andarranged in a cross-like form. However, there still is the same problemas described above with reference to FIG. 2D.

SUMMARY OF THE INVENTION

[0018] A general object of the present invention is to provide stackedsemiconductor devices and methods of producing the semiconductor devicesin which the above disadvantages are eliminated.

[0019] A more specific object of the present invention is to provide astacked semiconductor device in which a plurality of semiconductor chipsof desired sizes are stacked as one package.

[0020] Another specific object of the present invention is to provide amethod of producing such a semiconductor device.

[0021] The above objects of the present invention are achieved by astacked semiconductor device which comprises:

[0022] a first substrate that has external connecting terminals;

[0023] first terminals that are placed on a surface of the firstsubstrate opposite to a surface of the first substrate on which theexternal connecting terminals of the first substrate are formed;

[0024] at least one first semiconductor chip that is mounted on thefirst substrate;

[0025] a second substrate that is placed on the first semiconductorchip;

[0026] at least one second semiconductor chip that is mounted on thesecond substrate; and

[0027] second terminals that are formed on the second substrate andelectrically connected to at least one of the first semiconductor chipand the second semiconductor chip, the second terminals being connectedto the first terminals by wire bonding.

[0028] According to the above-mentioned invention, one of the first andsecond semiconductor chips is electrically connected directly to thefirst substrate provided with the external connecting electrodes, andthe other one is electrically connected to the first substrate via thesecond substrate. Accordingly, even if the first and secondsemiconductor chips are of the same size, one of the semiconductor chipscan be connected directly to first terminals of the first substrate,while the other can be electrically connected to the first substrate viasecond terminals of the second substrate by wire bonding. Also, if thesecond semiconductor chip is much smaller than the first semiconductorchip, the first semiconductor chip can be connected directly to thefirst terminals of the first substrate by wire bonding, and the secondsemiconductor chip can be electrically connected to the first terminalsof the first substrate via the second terminals of the second substrateby wire bonding. Accordingly, by simply employing the second substratebetween the first and second semiconductor chips, a plurality ofsemiconductor chips of desired sizes can be stacked as one package.

[0029] The above objects of the present invention are also achieved by astacked semiconductor device which comprises:

[0030] a first substrate that has external connecting terminals;

[0031] a plurality of semiconductor chips that are stacked on oneanother and mounted on the first substrate; and

[0032] second substrates that are interposed between the plurality ofsemiconductor chips,

[0033] wherein:

[0034] the plurality of semiconductor chips and the second substratesare placed on the first substrate;

[0035] each of the second substrates has an extending portion thatextends beyond an outer periphery of the semiconductor chip locatedimmediately above the second substrate;

[0036] the extending portion is provided with bonding pads thatare-electrically connected to at least one of the semiconductor chiplocated immediately above each second substrate and the semiconductorchip located immediately below the second substrate; and

[0037] the bonding pads are electrically connected to the firstsubstrate by wire bonding.

[0038] According to the above-mentioned invention, an arbitrary numberof semiconductor chips can be arranged on the first substrate andpackaged in a stacked state. For example, the semiconductor chips are ofthe same kind, and stacked in a direction perpendicular to the firstsubstrate. Additionally, the length of the extending portions of thesecond substrates may be increased toward the first substrate, and eachof the second substrate my be connected to another one of the secondsubstrates located immediately below from the uppermost second substrateto the lowermost second substrate, and the lowermost second substratemay be connected to the first substrate by wire bonding. Alternatively,the extending portions of the second substrates may have the samelength, and the each of the second substrates may be connected to thefirst substrate by wire bonding.

[0039] Additionally, the above objects of the present invention are alsoachieved by a stacked semiconductor device which comprises:

[0040] a first substrate that has external connecting terminals;

[0041] first terminals that are placed on a surface of the firstsubstrate opposite to a surface of the first substrate on which theexternal connecting terminals of the first substrate are formed;

[0042] at least one first semiconductor chip that is mounted on thefirst substrate;

[0043] a redistribution layer provided on the first semiconductor chip;

[0044] at least one second semiconductor chip that is mounted on theredistribution layer; and

[0045] a third semiconductor chip that is used-for testing at least oneof the first and second semiconductor chips, the third semiconductorchip being mounted on the redistribution layer,

[0046] wherein at least one of the first and second semiconductor chipis electrically connected to the first substrate via the redistributionlayer, and the third semiconductor chip is electrically connected to theredistribution layer.

[0047] According to the above-mentioned invention, the secondsemiconductor chip and the third semiconductor chip for testing aremounted on the first semiconductor chip via the redistribution layer.The third semiconductor chip has a test circuit used for testing thefirst and second semiconductor chips. Accordingly, the test circuit canbe easily incorporated into the semiconductor device. Additionally,there is no need to extend all of the electrodes of the first and secondsemiconductor chips toward the outside of the semiconductor device, andonly input and output terminals connected to the test circuit may beprovided to the semiconductor device. Thus, the test circuit can beincorporated into the semiconductor device without increasing the sizeof the semiconductor device.

[0048] Additionally, the above objects of the present invention are alsoachieved by a method of producing a stacked semiconductor device,comprising the steps of:

[0049] forming protruding electrodes on a first semiconductor chip;

[0050] mounting the first semiconductor chip on a second substrate byflip-chip bonding;

[0051] securing a second semiconductor chip, which is smaller than thesecond substrate, to a side of the second substrate opposite to a sideon which the first semiconductor chip is mounted, and securing the firstsemiconductor chip to a front surface of a first substrate;

[0052] connecting the first and second semiconductor chips to the firstsubstrate by wire bonding;

[0053] encapsulating the first and second semiconductor chips and thesecond substrate on the first substrate; and

[0054] forming external connecting electrodes on a back surface of thefirst substrate.

[0055] According to the above-mentioned method, the first semiconductorchip is mounted on the second substrate by flip-chip bonding, so thatthe electrodes of the first semiconductor chip can be electricallyconnected to the bonding pads formed on the opposite side of the secondsubstrate. The bonding pads are connected to the first substrate by wirebonding, so that the first semiconductor chip can be electricallyconnected to the first substrate. The second semiconductor chip issecured onto the second substrate, with the electrodes thereof facingupward, so that the second semiconductor chip can be connected directlyto the first substrate.

[0056] Additionally, the above objects of the present invention are alsoachieved by a method of producing a stacked semiconductor device,comprising the steps of:

[0057] securing a first semiconductor chip onto a front surface of afirst substrate;

[0058] securing a second substrate onto the first semiconductor chip;

[0059] securing a second semiconductor chip, which is smaller than thefirst semiconductor chip, onto the second substrate;

[0060] connecting the second semiconductor chip to the second substrateby wire bonding;

[0061] connecting the second substrate and the first semiconductor chipto the first substrate by wire bonding;

[0062] encapsulating the first and second semiconductor chips and thesecond substrate on the first substrate; and

[0063] forming external connecting electrodes on a back surface of thefirst substrate.

[0064] According to the above-mentioned method, the second semiconductorchip is connected to the second substrate by wire bonding, while thefirst semiconductor chip is connected to the first substrate.Accordingly, even if the second semiconductor chip is much smaller thanthe first semiconductor chip, the second semiconductor chip can beelectrically connected to the first substrate without increasing thelength of the bonding wires.

[0065] Other objects, features and advantages of the present inventionwill become more apparent from the following description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0066]FIG. 1 shows the structure of a conventional S-MCP in which twosemiconductor chips are stacked;

[0067]FIGS. 2A to 2D show the positional relationship between the uppersemiconductor chip and the lower semiconductor chip in the conventionalS-MCP;

[0068]FIG. 3 is a sectional view of a part of a stacked semiconductordevice in accordance with a first embodiment of the present invention;

[0069]FIGS. 4A to 4F illustrate production processes of the stackedsemiconductor device in accordance with the first embodiment of thepresent invention;

[0070]FIG. 5 shows a wiring example in which the two semiconductor chipsin the semiconductor device of the first embodiment are memory chips ofthe same type;

[0071]FIG. 6 is a schematic view of a part of bonding wires that embodythe wiring example shown in FIG. 5;

[0072]FIG. 7 shows a wiring example in which a change is made to thewiring example of FIG. 5 and the I/O configuration is doubled;

[0073]FIG. 8 is a schematic view of a part of bonding wires that embodythe wiring example shown in FIG. 7;

[0074]FIGS. 9A and 9B show semiconductor devices in each of which aplurality of semiconductor chips are stacked in accordance with thefirst embodiment of the present invention;

[0075]FIG. 10 is a sectional view of a part of a stacked semiconductordevice in accordance with a second embodiment of the present invention;

[0076]FIG. 11 is a perspective view showing the stacked structure of thestacked semiconductor device in accordance with the second embodiment ofthe present invention;

[0077]FIGS. 12A to 12E illustrate the production processes of thestacked semiconductor device in accordance with the second embodiment ofthe present invention;

[0078]FIG. 13 is a sectional view of a semiconductor device having aplurality of upper semiconductor chips;

[0079]FIG. 14A is a plan view of an interior (a quarter part) of a firstvariation of the semiconductor device shown in FIG. 13; FIG. 14B is across-sectional view taken along a line XIV-XIV of FIG. 14A;

[0080]FIG. 15A is a plan view of an interior (a quarter part) of asecond variation of the semiconductor device shown in FIG. 13; FIG. 15Bis a cross-sectional view taken along a line XV-XV of FIG. 15A;

[0081]FIG. 16A is a plan view of an interior (a quarter part) of a thirdvariation of the semiconductor device shown in FIG. 13; FIG. 16B is across-sectional view taken along a line XVI-XVI of FIG. 16A;

[0082]FIG. 17A is a plan view of an interior (a quarter part) of afourth variation of the semiconductor device shown in FIG. 13; FIG. 17Bis a cross-sectional view taken along a line XVII-XVII of FIG. 17A;

[0083]FIG. 18 is a plane view showing a state in which a flexibleprinted wiring boar is stacked on a lower semiconductor chip;

[0084]FIG. 19 is a perspective view showing cut surfaces off extendingportions shown in FIG. 18;

[0085]FIG. 20 is a side view of a part of a semiconductor device inwhich a metal layer if provided on a second substrate;

[0086]FIG. 21A is a cross-sectional view of a semiconductor devicehaving no test terminal; FIG. 21B is a cross-sectional view of asemiconductor device having test terminals;

[0087]FIG. 22A is a cross-sectional view of a semiconductor devicehaving a lower semiconductor chip having no test circuit; FIG. 22B is across-sectional view of a semiconductor chip having a lowersemiconductor chip having test circuit;

[0088]FIG. 23A is a cross-sectional view of a semiconductor devicehaving an upper semiconductor chip having no test circuit; FIG. 23B is across-sectional view of a semiconductor chip having an uppersemiconductor chip having test circuit;

[0089]FIG. 24 is a cross-sectional view of a stacked semiconductordevice according to a third embodiment of the present invention;

[0090]FIG. 25 is a cross-sectional view of a first variation of thesemiconductor device according to the third embodiment of the presentinvention;

[0091]FIG. 26 is a cross-sectional view of a second variation of thesemiconductor device according to the third embodiment of the presentinvention; and

[0092]FIG. 27 is a cross-sectional view of a third variation of thesemiconductor device according to the third embodiment of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0093] The following is a description of embodiments of the presentinvention, with reference to the accompanying drawings.

[0094] Referring now to FIGS. 3 and 4A to 4F, a first embodiment of thepresent invention will be described below.

[0095] As shown in FIG. 3, a semiconductor device 20 of the firstembodiment of the present invention comprises two semiconductor chips 22and 24 of the same type that are laminated and packaged. The lowersemiconductor chip 22 is mounted on a flexible printed circuit board 26as a first substrate, with the surface provided with electrodes facingupward. Accordingly, the backside face of the semiconductor chip 22 isbonded to the flexible printed wiring board 26 by an adhesive 28.

[0096] The flexible printed wiring board 26 is larger than thesemiconductor chip 22, and has bonding pads 26 c on the surface 26 a onwhich the semiconductor chip 22 is mounted. The bonding pads 26 c areelectrically connected to soldering balls 30 formed as externalconnecting protruding electrodes on the reverse surface 26 b of theflexible printed wiring board 26.

[0097] A printed circuit board 32 as a second substrate is placed on thesemiconductor chip 22, and the semiconductor chip 22 is attached to theprinted circuit board 32 by flip-chip bonding. More specifically,protruding electrodes (bumps) 34 are formed on electrodes 22 a of thesemiconductor chip 22, and the protruding electrodes 34 are connected toelectrode pads 32 b formed on the reverse surface 32 a of the printedcircuit board 32 by flip-chip bonding. On the surface 32 c of theprinted circuit board 32, bonding pads 32 d are formed and electricallyconnected to the electrode pads 32 b. Accordingly, the electrodes 22 aof the semiconductor chip 22 are electrically connected to the bondingpads 32 d via the protruding electrodes 34 and the electrode pads 32 b.

[0098] The semiconductor chip 24 is fixed onto the surface 32 of theprinted circuit board 32 by an adhesive 36, with the surface providedwith electrodes 24 a facing upward. The electrodes 24 a of thesemiconductor chip 24 are electrically connected to the bonding pads 26c of the flexible printed wiring board 26 by bonding wires 38 a. Thebonding pads 32 d of the printed circuit board 32 are electricallyconnected to the bonding pads 26 c of the flexible printed wiring board26 by bonding wires 38 b.

[0099] As described above, the stacked semiconductor chips 22 and 24, aswell as the bonding wires 38 a and 38 b, are encapsulated by anencapsulation resin 40, thereby forming the packaged semiconductordevice 20.

[0100] Since the electrodes 22 a of the semiconductor chip 22 areelectrically connected to the bonding pads 32 d via the protrudingelectrodes 34 and the electrode pads 32 b, the electrodes 22 a of thesemiconductor chip 22 and the electrodes 24 a of the semiconductor chip24 are electrically connected to the bonding pads 26 c of the flexibleprinted wiring board 26. Accordingly, the electrodes 22 a of thesemiconductor chip 22 and the electrodes 24 a of the semiconductor chip24 are electrically connected to the soldering balls 30 via the bondingpads 26 c.

[0101] In the above structure, the printed circuit board 32 interposedas the second substrate between the semiconductor chips 22 and 24 islarger than the upper semiconductor chip 24 so as to prevent the uppersemiconductor chip 24 from covering the bonding pads 32 d. The printedcircuit board 32 as the second substrate has an extending portion 33extending from the outer periphery of the upper semiconductor chip 24,and the bonding pads 32 d are formed at the extending portion 33.

[0102] Being of the same type, the semiconductor chips 22 and 24 areequal in size. Accordingly, the semiconductor chips 22 and 24 are placedat the same locations as the surface 32 c and the reverse surface 32 aof the printed circuit board 32, so that the center of the printedcircuit board 32 is sandwiched by the semiconductor chips 22 and 24,with only the outer peripheral portions extending from the outerperipheries of the semiconductor chips 22 and 24. The bonding pads 32 dfor connecting with the electrodes 22 a of the semiconductor chip 22 arelocated at the extending portion 33 of the printed circuit board 32.

[0103] When the bonding wires 38 a are connected to the bonding pads 32d of the printed circuit board 32, the capillary of a wire bonder needsto be placed immediately above the bonding pads 32 d. Therefore, thelength of the extending portion 33 of the printed circuit board 32 hasto be long enough to place the capillary immediately above the bondingpads 32 d.

[0104] When the bonding wires 38 a are connected to the bonding pads 23d, the end portions of bonding wires extending from the capillary arepressed against the bonding pads 32 d. Since the extending portion 33 ofthe printed circuit board 32 is not supported from below, the extendinglength should preferably small so as to prevent deformation and damageby the pressing force of the bonding wires extending from the capillary.

[0105] In view of this, the extending length of the printed circuitboard 32 extending from the semiconductor chips 22 and 24 is set to sucha length that the capillary can be arranged, and that the extendingportion 33 of the printed circuit board 32 can be prevented from beingdamaged by the pressing force at the time of wire bonding. Also, thematerial of the printed circuit board 32 should have enough rigidity toendure a certain pressing force.

[0106] The bonding pads 26 c, to which the bonding wires 38 a and 38 bare connected, are formed on the flexible printed wiring board 26. Sincethe bonding pads 26 c should be placed in an outer region of the printedcircuit board 32, the flexible printed wiring board 26 needs to belarger than the printed circuit board 32.

[0107] Referring now to FIGS. 4A to 4F, the production processes of thestacked semiconductor device 20 of the first embodiment will bedescribed below.

[0108] To produce the stacked semiconductor device 20, the bumps 34 arefirst formed at the electrodes 22 a of the lower semiconductor chip 22,as shown in FIG. 4A. The semiconductor chip 22 is then mounted on theprinted circuit board 32 by flip-chip bonding, as shown in FIG. 4B.

[0109] Next, as shown in FIG. 4C, the reverse face of the lowersemiconductor chip 22 is bonded to the surface 26 a of the flexibleprinted wiring board 26 by the adhesive 28, and the upper semiconductorchip 24 is bonded to the surface 32 c of the printed circuit board 32 inconformity with the position of the lower semiconductor chip 22 by theadhesive 36.

[0110] As shown in FIG. 4D, the electrodes 22 a of the semiconductorchip 22 are connected to the bonding pads 26 c by the bonding wires 38b, and the electrodes 24 a of the semiconductor chip 24 are connected tothe bonding pads 26 c by the bonding wires 38 a. Here, the semiconductorchips 22 and 24 are of the same type, as mentioned later, and anyelectrode that can be commonly used between the semiconductor chips 22and 24 is connected to the same bonding pad 26 c.

[0111] As shown in FIG. 4E, the semiconductor chips 22 and 24, as wellas the bonding wires 38 a and 38 b, are encapsulated by theencapsulation resin 40. Ss shown in FIG. 4F, the soldering balls 30 areformed as the external connecting protruding electrodes on the reverseface 26 b of the flexible printed wiring board 26, thereby completingthe stacked semiconductor device 20.

[0112] In the stacked semiconductor device 20 of this embodiment, thelower semiconductor chip 22 and the upper semiconductor chip 24 are ofthe same type and the same size. The printed circuit board 32 interposedas the second substrate between the semiconductor chips 22 and 24 helpsto connects the electrodes 22 a of the lower semiconductor chip 22 tothe bonding pads 26 c of the flexible printed wiring board 26 as thefirst substrate. By this simple addition of the printed circuit board32, semiconductor chips of the same type can be stacked and packagedinto one semiconductor device.

[0113]FIG. 5 shows a wiring example in which the semiconductor chips 22and 24 are memory chips of the same type (I/O configuration: 8 bits×2=16bits). With the wiring structure shown in FIG. 5, the memory capacitycan be doubled without making any change to the I/O configuration. InFIG. 5, a memory 1 represents a memory chip equivalent to the lowersemiconductor chip 22, and a memory 2 represents a memory chipequivalent to the upper semiconductor chip 24. Although the memory 2 isactually placed on the memory 1, the memory 1 and the memory 2 arealigned in FIG. 2 for ease of explanation.

[0114] The memory 1 and the memory 2 each have a lower 8-bit I/Oterminal, an upper 8-bit I/O terminal, a /BYTE terminal, an Addressterminal, and other terminals. The memory 1 further includes a /CE#1terminal (a chip enable terminal) and a VCC#2 terminal, while the memory2 further includes a /CE#2 terminal (a chip enable terminal) and a VCC#2terminal. Among these terminals, the lower 8-bit I/O terminal, the upper8-bit I/O terminal, the /BYTE terminal, the Address terminal, and theother terminals can receive signals common to both the memory 1 and thememory 2. Accordingly, the lower 8-bit I/O terminal, the upper 8-bit I/Oterminal, the /BYTE terminal, the Address terminal, and the otherterminals are connected to the same external connecting terminals(soldering balls) 30 of the semiconductor device 20. Thus, thecorresponding terminals between the memory 1 and the memory 2 areconnected to the same bonding pads 26 c of the flexible printed wiringboard 26 by the bonding wires 38 a and 38 b.

[0115] Meanwhile, among those terminals, the /CE#1 terminals (the chipenable terminal) and the VCC#1 terminals of the memory 1 are connectedto external connecting terminals different from the external connectingterminals to which the /CE#2 terminal (the chip enable terminal) and theVCC#2 terminal are connected, so that the memory 1 and the memory 2 canbe controlled independently of each other. Since the chip enableterminals of the memory 1 and the memory 2 receive signals independentlyof each other, the chip enable terminals are connected to differentexternal connecting terminals. The /CE#1 terminal of the memory 1 isconnected to a /CE#1 terminal of the semiconductor device 20, while the/CE#2 terminal of the memory 2 is connected to a /CE#2 terminal of thesemiconductor device 20, so as to receive separate signals. The VCC#1terminal of the memory 1 and the VCC#2 terminal of the memory 2 may beconnected to a common external connecting terminal, but the VCC#1terminal and the VCC#2 terminal are connected in separate externalconnecting terminals in this embodiment.

[0116]FIG. 6 is a schematic view of a part of the bonding wires thatembody the wiring example shown in FIG. 5. In FIG. 6, terminals DQ0,DQ8, DQ1, and DQ9 among the lower 8-bit I/O terminals (equivalent to theelectrodes 24 a) of the upper memory 1 are shown. The bonding pads 32 dconnected to terminals DQ0, DQ8, DQ1, and DQ9 of the lower memory 2 areshown on the printed circuit board 32 as the second substrate.

[0117] The terminals DQ0, DQ8, DQ1, and DQ9 of the memory 1 and thememory 2 can receive common signals, and can be connected to the sameterminals of the flexible printed wiring board 26 as the firstsubstrate. For instance, the terminal DQ0 of the upper memory 1 and thebonding pad connected to the terminal DQ0 of the lower memory 2 areconnected to the same bonding pad 26 c of the flexible printed wiringboard 26.

[0118] The bonding wire 38 a that connects the terminal DQ0 of the uppermemory 1 and one of the bonding pads 26 c deviates in the heightdirection from the bonding wire 38 b that connects the bonding pad 32 dconnected to the terminal DQ2 of the lower memory 2 and the bonding pad26 c, so as to prevent contact between the bonding wires 38 a and 38 b,as shown in FIG. 3. In the example shown in FIG. 6, the location of eachbonding pad 32 d deviates in the horizontal direction from the bondingwires 38 a, so that the contact between the bonding wires 38 a and 38 bcan be surely prevented.

[0119]FIG. 7 shows an example in which a change is made to the wiring inthe memory 1 and the memory 2, and the I/O configuration is doubled.More specifically, in the wiring example shown in FIG. 7, the lower8-bit I/O terminals and the upper 8-bit I/O terminals are not commonlyconnected, but separately connected to different external connectingterminals (soldering balls) of the semiconductor device 20. Accordingly,the lower 8-bit I/O terminals and the upper 8-bit I/O terminals areconnected to separate bonding pads 26 c of the flexible printed wiringboard 26 by the bonding wires 38 a and 38 b.

[0120] In case only one of the memory 1 and the memory 2 is used, the/CE#1 terminal (the chip enable terminal) and the VCC#1 terminal of thememory 1 are connected to external connecting terminals that aredifferent from the external connecting terminals to which the /CE#2terminal (the chip enable terminal) and the VCC#2 terminal of the memory2. Also, the /BYTE terminal is connected in the package as a DWORDterminal to one terminal. The DWORD terminal functions to switch the I/Oconfiguration between a 16-bit configuration and a 32-bit configuration.The rest of the terminals can be connected to common external connectingterminals.

[0121]FIG. 8 is a schematic view of a part of the bonding wires thatembody the wiring example shown in FIG. 7. In FIG. 8, the terminals DQ0,DQ8, DQ1, and DQ9 among the lower 8-bit I/O terminals (equivalent to theelectrodes 22 a) of the upper memory 1 are shown. On the printed circuitboard 32 as the second substrate, the bonding pads 32 d connected to theterminals DQ0, DQ8, DQ1, and DQ9 of the lower memory 2 are shown.

[0122] Since the terminals DQ0, DQ8, DQ1, and DQ9 of the memory 1 andthe memory 2 receive separate signals, they are connected to differentboning pads. For instance, the terminal DQ0 of the upper memory 1 isconnected as a DQ terminals to one of the bonding pad 26 c of theflexible printed wiring board 26, while the bonding pad connected to theDQ0 terminal of the lower memory 2 is connected as a DQ8 terminal toanother one of the bonding pads 26 c.

[0123] The bonding wire 38 a that connects the terminal DQ0 of the uppermemory 1 and the corresponding bonding pad 26 c and the bonding wire 38b that connects the bonding pad 32 d connected to the terminal DQ0 ofthe lower memory 2 and the bonding pad 26 c corresponding to theterminal DQ8 are arranged in such a manner that the bonding pad 32 ddeviates in the horizontal direction from the bonding wires 38 a and 38b. In this manner, the bonding wires 38 a and 38 b are situated inparallel with each other, and contact between the bonding wires 38 a and38 b can be prevented.

[0124] The bonding wire 38 a that connects the terminals (electrodes) ofthe upper memory 1 and the bonding pads 26 c of the flexible printedwiring board 26 should be located so as not to be brought into contactwith the printed circuit board 32. In the example shown in FIG. 8, theprinted circuit board 32 is provided with the notches 32 e, so that thebonding wires 38 a extends along the notches 32 e. In this structure,the bonding wires 38 a can be shortened, and the contact of the bondingwires 38 a with the surrounding components can be prevented. Also, thecontact of the capillary of wire bonding device with the printed circuitboard 32 can be prevented.

[0125]FIGS. 9A and 9B show examples in each of which a plurality ofsemiconductor chips are stacked in accordance with the first embodimentof the present invention. In each of the two examples, foursemiconductor chips of the same type are stacked, and second substratesare interposed between the semiconductor chips. At the end of thestacking process, only the electrodes of the uppermost semiconductorchip are exposed, and the other semiconductor chips are mounted on thesecond substrates (the printed circuit boards 32) by flip-chip bonding.

[0126] A semiconductor device 50 shown in FIG. 9A comprises foursemiconductor chips 52-1 to 52-4 of the same type that are stacked andthen connected to one another by wire bonding. This wire bonding processis performed first between the uppermost semiconductor chip 52-4 and theuppermost second substrate 32-3, and then performed between theuppermost second substrate 32-3 and the second substrate 32-2immediately below the second substrate 32-3. In this manner, the wirebonding process is successively performed until the wire bonding betweenthe lowermost second substrate 32-1 and the first substrate (theflexible printed wiring board 26). To perform collectively the wiringbonding process, each second substrate needs to be larger than thesecond substrate located immediately above, so as to prevent the bondingpads from being covered by the upper second substrate.

[0127] In a semiconductor device 60 shown in FIG. 9B, semiconductorchips 62-1 to 62-4 are stacked one by one, and the-wire bonding processis performed for the each stacking process. More specifically, thelowermost semiconductor chip 62-1 is mounted on the first substrate (theflexible printed wiring board 26), and the lowermost second substrate32-1 is then mounted on the lowermost semiconductor chip 621 byflip-chip bonding. At this point, a wire bonding process is performedbetween the second substrate 32-1 and the first substrate 26. Next, thesecond lowermost semiconductor chip 62-2 is secured onto the lowermostsecond substrate 32-1, and the second lowermost second substrate 32-2 ismounted on the semiconductor chip 62-2 by flip-chip bonding. A wirebonding process is then performed between the second lowermost secondsubstrate 32-2 and the first substrate 26. In this manner, a wirebonding process is performed every time one second substrate is stackedon one semiconductor chip. When the uppermost semiconductor chip 62-4 isstacked on and connected to the uppermost second substrate 32-3 by wirebonding, all the wire bonding processes are completed. In thisstructure, all the second substrates can have the same size.

[0128] In the above embodiment, the electrodes to be connected by wiresare arranged along the two opposite sides of each semiconductor chip.However, it is also possible to arrange the electrodes along the foursides of each semiconductor chip. Also, each second substrate (theprinted circuit board 32) should preferably be made of a material havingrigidity, but a flexible printed wiring board maybe employed so as toreduce the width of the package, as long as enough substrate strengthcan be maintained.

[0129] Next, a stacked semiconductor device in accordance with a secondembodiment of the present invention will be described.

[0130]FIG. 10 is a sectional view of a part of the stacked semiconductordevice in accordance with the second embodiment of the presentinvention. FIG. 11 is a perspective view showing the stacked structureof the stacked semiconductor device in accordance with the secondembodiment of the present invention. FIGS. 12A to 12E show theproduction processes of the stacked semiconductor device in accordancewith the second embodiment of the present invention. In FIGS. 10 to 12E,the same components as in FIG. 3 are denoted by the same referencenumerals, and explanations for those components are omitted in thefollowing description.

[0131] As shown in FIG. 10, a semiconductor device 70 of the secondembodiment of the present invention has two semiconductor chips 72 and74 of different sizes stacked in one package. The lower semiconductorchip 72 is mounted on the flexible printed wiring board 26 as the firstsubstrate, with the surface provided with electrodes 72 a facingdownward. Thus, the reverse surface of the semiconductor chip 72 isbonded to the flexible printed wiring board 26 by the adhesive 28.

[0132] The flexible printed wiring board 26 is larger than thesemiconductor chip 72 mounted thereon, and the bonding pads 26 c areformed on the surface 26 a on which the semiconductor chip 72 ismounted. The bonding pads 26 c are electrically connected to thesoldering balls 30 formed as external connecting protruding electrodeson the reverse surface 26 b of the flexible printed wiring board 26.

[0133] A flexible printed wiring board 76 is placed as a secondsubstrate on the semiconductor chip 72, and secured there by an adhesive78. Bonding pads 76 d and 76 b are formed on the surface 76 c of theflexible printed wiring board 76. The bonding pads 76 d are formed atthe peripheral portion of the flexible printed wiring board 76, whilethe bonding pads 76 b are arranged in a region surrounding the positionin which the semiconductor chip 74 is to be placed within the area ofthe flexible printed wiring board 76. The bonding pads 76 d areelectrically connected to the corresponding bonding pads 76 b by awiring pattern 76 e. The semiconductor chip 74 is secured onto thesurface 76 c of the flexible printed wiring board 76 by an adhesive 80,with the surface provided with electrodes 74 a facing upward.

[0134] In the above stacked structure, the electrodes 74 a of the uppersemiconductor chip 74 are electrically connected to the bonding pads 76b of the flexible printed wiring board 76 by bonding wires 82.Meanwhile, the bonding pads 76 d are connected to the bonding pads 26 cof the flexible printed wiring board 26 by bonding wires 84.

[0135] As described above, since the bonding pads 76 b are electricallyconnected to the bonding pads 76 d by the wiring pattern 76 e on theflexible printed wiring board 76, the electrodes 74 a of thesemiconductor chip 74 are electrically connected to the bonding pads 26c of the flexible printed wiring board 26 via the bonding wires 82, thebonding pads 76 b, the wiring pattern 76 e, the bonding pads 76 d, andthe bonding wires 84.

[0136] Meanwhile, the electrodes 72 a of the lower semiconductor chip 72is electrically connected to the bonding pads 26 c of the flexibleprinted wiring board 26 by bonding wires 86.

[0137] The semiconductor chips 72 and 74 stacked as described above areencapsulated by the encapsulation resin 40, together with the bondingwires 82, 84, and 86, thereby constituting the packaged semiconductordevice 70.

[0138] As described above, the electrodes 72 a of the semiconductor chip72 and the electrodes 74 a of the semiconductor chip 74 are electricallyconnected to the bonding pads 26 c of the flexible printed wiring board26. Accordingly, the electrodes 72 a of the semiconductor chip 72 andthe electrodes 74 a of the semiconductor chip 74 are electricallyconnected to the soldering balls 30 as the external connecting terminalsvia the bonding pads 26 c.

[0139] In the above stacked structure, the flexible printed wiring board76 formed as the second substrate on the lower semiconductor chip 72 islocated in an inner position compared with the location of theelectrodes 72 a of the lower semiconductor chip 72. More specifically,the end portion of the flexible printed wiring board 76 is designed in-such a manner that the capillary of a wire bonding device can beprevented from being brought into contact with the end portion of theflexible printed wiring board 76 when the wire bonding device performs awire bonding process on the electrodes 72 a.

[0140] The bonding pads 76 b of the flexible printed wiring board 76 arelocated in positions in accordance with the size of the semiconductorchip 74. The bonding pads 76 are formed at such locations that a wireboding process can be easily performed between the bonding pads 76 b andthe electrodes 74 a of the semiconductor chip 74. More specifically, thebonding pads 76 b are formed at an extending portion 77 that extendsbeyond the outer periphery of the upper semiconductor chip 74, so thatthe bonding pads 76 d can be easily bonded by wires to the flexibleprinted wiring board 26, which is the first substrate.

[0141] The second substrate used in this embodiment is the flexibleprinted wiring board 76, which does not necessarily have rigidity. Sincethe entire second substrate is mounted on and supported by the lowersemiconductor chip 72 in this embodiment, the second substrate may beflexible.

[0142] As shown in FIG. 11, although the upper semiconductor chip 74 ismuch smaller than the lower semiconductor chip 72 in this embodiment,the flexible printed wiring board 76, which is the second substrate, caneffectively connect the electrodes 74 a of the upper semiconductor chip74 to the bonding pads 26 c of the flexible printed wiring board 26,which is the first substrate.

[0143] The wiring pattern 76 e of the flexible printed wiring board 76can be designed with certain freedom. For instance, the bonding padscorresponding to the electrodes formed at one side of the semiconductorchip 76 can be pulled around to the opposite side.

[0144] Referring now to FIGS. 12A to 12E, the production processes ofthe semiconductor device 70 shown in FIG. 10 will be described below.

[0145] As shown in FIG. 12A, the flexible printed wiring boards 26 and76, and the semiconductor chips 72 and 74 are prepared. As shown in FIG.12B, the flexible printed wiring boards 26 and 76, and the semiconductorchips 72 and 74 are stacked and secured by the adhesives 28, 78, and 80.

[0146] As shown in FIG. 12C, the electrodes 74 a of the uppersemiconductor chip 74 are electrically connected to the bonding pads 76b of the flexible printed wiring board 76 by the bonding wires 82. Also,the electrodes 72 a of the lower semiconductor chip 72 are electricallyconnected to the bonding pads 26 c of the flexible printed wiring board26 by the bonding wires 84. Further, the bonding pads 76 d of theflexible printed wiring board 76 are electrically connected to thebonding pads 26 c of the flexible printed wiring board 26 by the bondingwires 86.

[0147] After the wire bonding process, the semiconductor chips 72 and74, together with the bonding wires 82, 84, and 86, are encapsulated bythe encapsulation resin 40, as shown in FIG. 12D. As shown in FIG. 12E,the soldering balls 30 formed as the external connecting protrudingelectrodes on the reverse surface 26 b of the flexible printed wiringboard 26, thereby completing the stacked semiconductor device 70.

[0148] In the semiconductor device shown in FIG. 10, one semiconductorchip is stacked on the lower semiconductor chip via a flexible printedwiring board. However, if the upper semiconductor chip is much smallerthan the lower semiconductor chip, a plurality of semiconductor chipsmay be stacked on the lower semiconductor chip via a flexible printedwiring board, as shown in FIG. 13.

[0149] In a semiconductor device 90 shown in FIG. 13, two semiconductorchips 74-1 and 74-2 are placed on the lower semiconductor chip 72 viathe flexible printed board 76. The structure and the method of thesemiconductor device 90 are substantially the same as the semiconductordevice 70 shown in FIG. 10, and explanations for those are omitted inthis description.

[0150] In each of the stacked semiconductor devices 70 and 90 of thisembodiment, the lower semiconductor chip 72 is much larger than theupper semiconductor chip 74 or the upper semiconductor chips 74-1 and74-2. However, the flexible printed wiring board 76 as the secondsubstrate formed between the lower semiconductor chip 74 and the uppersemiconductor chip 74 or the upper semiconductor chips 74-1 and 74-2connects the electrodes 72 a of the lower semiconductor chip 72 to thebonding pads 26 c of the flexible printed wiring board 26 as the firstsubstrate via the flexible printed wiring board 76. Accordingly, thesimple addition of the flexible printed wiring board enables a pluralityof semiconductor chips of different types and sizes to be stacked andturned into one packaged.

[0151] Although the electrodes to be connected by wires are arrangedalong to opposite sides of each semiconductor chip in the aboveembodiment, it is also possible to arrange the electrodes along the foursides of each semiconductor chip.

[0152] The lower semiconductor chip 72 is connected to the flexibleprinted wiring board 26 by wire bonding in this embodiment. However, itis possible to form protruding electrodes on the lower semiconductorchip 72, and connect the lower semiconductor chip 72 to the flexibleprinted wiring board 76 by flip-chip bonding, as in the first embodimentof the present invention. In such a case, the lower semiconductor chip72 is electrically connected to the flexible wiring board 26 via theflexible printed wiring board 76.

[0153] The second substrate of this embodiment is the flexible printedwiring board, which is flexible and can have a film-like form. However,it is possible to employ a printed circuit board made of a materialhaving rigidity.

[0154] In the semiconductor device 90 shown in FIG. 13, not only theupper semiconductor chip but also the lower semiconductor chip can bepluralized.

[0155] A description will now be given, with reference to FIGS. 14through 17, of various variations of the semiconductor device accordingthe second embodiment of the present invention shown in FIG. 10. FIGS.14A and 14B show a first variation of the semiconductor device 90. FIG.14A is a plan view of an interior (a quarter part) of the firstvariation, and FIG. 14B is a cross-sectional view taken along a lineXIV-XIV of FIG. 14A. FIGS. 15A and 15B show a second variation of thesemiconductor device 90. FIG. 15A is a plan view of an interior (aquarter part) of the second variation, and FIG. 15B is a cross-sectionalview taken along a line XV-XV of FIG. 15A. Additionally, FIGS. 16A and16B show a third variation of the semiconductor device 90. FIG. 16A is aplan view of an interior (a quarter part) of the third variation, andFIG. 16B is a cross-sectional view taken along a line XVI-XVI of FIG.16A. Further, FIGS. 17A and 17B show a fourth variation of thesemiconductor device 90. FIG. 17A is a plan view of an interior (aquarter part) of the fourth variation, and FIG. 17B is a cross-sectionalview taken along a line XVII-XVII of FIG. 17A.

[0156] The first variation shown in FIGS. 14A and 14B has basically thesame structure as the semiconductor device 70 shown in FIG. 10 exceptfor bonding wires 84A being added so as to connect the bonding pads 76 dof the flexible printed wiring board 76 to the electrodes 72 a of thelower semiconductor chip 72. That is, in the first variation shown inFIG. 14, the lower semiconductor chip 72 is mounted on the flexibleprinted wiring board 16 in a face-up state and connected bywire-bonding, and the upper semiconductor chip 74 is mounted on thelower semiconductor chip 72 via the flexible printed wiring board 76 ina face-up state and connected by wire-bonding. The bonding wires 84A areprovided to electrically connects the upper semiconductor chip 74 to thelower-semiconductor chip 72. Accordingly, the length of the signaltransmission path between the upper semiconductor chip 74 and the lowersemiconductor chip 72 is reduced, which enables a high-speed signaltransmission.

[0157] The second variation shown in FIGS. 15A and 15B has basically thesame structure as the semiconductor device 70 shown in FIG. 10 exceptfor the lower semiconductor chip 72 being mounted to the flexibleprinted wiring board 26 in a face-down state. That is, the lowersemiconductor chip 72 is mounted to the flexible printed wiring board 26by flip-chip bonding, and the upper semiconductor chip 74 is mounted onthe lower semiconductor chip 72 via the flexible printed wiring board 76and connected by wire-bonding.

[0158] The third variation shown in FIGS. 16A and 16B has basically thesame structure as the semiconductor device 70 shown in FIG. 10 exceptfor the upper semiconductor chip 74 being mounted to the flexibleprinted wiring board 76 in a face-down state. That is, the uppersemiconductor chip 74 is mounted to the flexible printed wiring board 76by flip-chip bonding, and the lower semiconductor chip 72 is mounted tothe flexible printed wiring board 26 and connected by wire bonding.

[0159] The fourth variation shown in FIGS. 17A and 17B is a combinationof the second variation and the third variation in which both the uppersemiconductor chip 74 and the lower semiconductor chip 72 are mounted ina face-down state. That is, the upper semiconductor chip 74 is mountedto the flexible printed wiring board 76 by flip-chip bonding, and thelower semiconductor chip 72 is mounted to the flexible printed wiringboard 26 also by flip-chip bonding.

[0160] In the semiconductor devices according to the above-mentionedsecond embodiment and its variations, an effect of discharging waterfrom inside the semiconductor device during a solder reflow process canbe achieved by constituting the flexible printed wiring board 76 (secondsubstrate) as shown in FIG. 18. FIG. 18 is a plane view showing a statein which the flexible printed wiring boar 76 is stacked on the lowersemiconductor chip 72.

[0161] In the manufacturing process of the semiconductor deviceaccording to the present invention, a plurality of lower semiconductorchip 72 may be arranged adjacent to each other and the flexible printedwiring board 76 and the upper semiconductor chip 74 may be stacked oneach of the lower semiconductor chip 72. The upper and lowersemiconductor chips 74 and 72 are encapsulated by the encapsulationresin, and then the thus-manufactured semiconductor devices areseparated from each other by dicing. In such as case, a plurality offlexible printed wiring board 76 as the second substrate are supplied inthe form of a single sheet

[0162] If the flexible printed wiring boards 76 in a single sheet areconnected at their four corners as shown in FIG. 18, an extendingportion 76A which connects the adjacent ones of the flexible printedwiring boards 76 is cut along a cutting line (dicing line) to separatethe semiconductor devices. Accordingly, as shown in FIG. 19, the endsurface (cutting surface) of the extending portion 76A of the secondsubstrate that has been cut is exposed in the side surface of theseparated semiconductor device.

[0163] If the end surface of the extending portion 76A of the flexibleprinted wiring board 76 as the second substrate is exposed from theencapsulation resin 40 of the semiconductor device, water existinginside the semiconductor device moves along the interface between theextending portion 76A and the encapsulation resin 40 during a solderreflow process, and discharged from the side surface of thesemiconductor device. Thus, generation of a void inside thesemiconductor device due to evaporation of the water during a solderreflow process can be prevented, thereby improving the reliability ofthe semiconductor device.

[0164] It should be noted that the position of the extending portion 76Ais not limited to the four corners of the flexible printed wiring board76, and is positioned at any position along the sides of the flexibleprinted wiring board 76. In FIG. 19, one of the cut surfaces of theextending portions 76A positioned in the middle corresponds to the oneprovided to one of the four corners of the flexible printed wiring board76. The cut surfaces on the left and right sides correspond to theextending portions being provided to the sides of the flexible printedwiring board 76.

[0165] Moreover, heat of the semiconductor chips 72 and 74 can bediffused and released by providing a layer of a material having a goodthermal conductivity, such as a metal layer 76B as shown in FIG. 20, onan entire surface of the flexible printed wiring board 76 as the secondsubstrate. Thereby, the temperature inside the semiconductor device canbe averaged even if there is a large, local heat generation, and a localtemperature rise can be prevented. Moreover, the heat releasing effectof the extending portion 76 can be further improved.

[0166] In the above-mentioned embodiments, the semiconductor chipsstacked in the semiconductor device may be connected to each other inthe package. For example, the upper semiconductor chips 74-1 and 74-2shown in FIG. 13 can be merely connected to the lower semiconductor chip72 via the flexible printed wiring board 76. Generally, in the stackedsemiconductor device, there is a case in which the semiconductor chip isoperated only inside the semiconductor device and there is no need toprovided external connections.

[0167] However, after the semiconductor chip is packaged as asemiconductor device, each semiconductor device must be subjected to atest so as to check its function. In order to conduct such as test, anexternal test circuit must be connected to each semiconductor device.Since the semiconductor chip that functions only in the semiconductordevice does not need terminals for external connection, the externalterminals are provided only for the test. That is, the semiconductordevice is provided with test terminals that are exclusively used for atest, which results in an increase in the size of the semiconductordevice.

[0168]FIG. 21A is a cross-sectional view of a semiconductor devicehaving no test terminal. FIG. 21B is a cross-sectional view of asemiconductor device having test terminals. Although each of thesemiconductor devices shown in FIGS. 21A and 21B has a lowersemiconductor chips 102 and an-upper semiconductor chip 104 of the samesize, the size of the semiconductor device shown in FIG. 21A isincreased due to formation of the test terminals 106A on a substrate 108in addition to regular terminals 106.

[0169] Accordingly, a semiconductor device having a test circuit thereinhas been suggested so as to provide a self diagnosis function. The selfdiagnosis technique is generally referred to as Built in Self Test(BIST), and the purpose of the BIST is to facilitate a test ofsemiconductor devices. By using a semiconductor device according to theBIST technique, there is no need to provide the test terminals, whichprevents the increase in the size of the semiconductor device due to theincrease in the number of terminals. However, in order to use the BISTtechnique, it must be considered as to whether or not the test circuitis incorporated at the development stage of the semiconductor device.Especially, when a plurality of semiconductor chips are stacked, thecombination of the semiconductor chips must be considered at thedevelopment stage. Accordingly, when the BIST technique is used, thetest circuit to be incorporated must be determined in consideration withthe stacking of semiconductor chips from the design stage of thesemiconductor device, which requires considerable time and labor for thedesign of the semiconductor device. Moreover, there is a problem in thatit is difficult to use the BIST technique for a conventional structurein which semiconductor chips have been already combined.

[0170] Additionally, the size of the semiconductor chip is increased dueto the incorporation of the test circuit in the semiconductor deviceeven when the number of terminals is reduced by using the BISTtechnique. For example, as shown in FIGS. 22A and 22B, when the testcircuit is incorporated into a lower semiconductor chip 102 on which asemiconductor chip is stacked, the size of the substrate 108 increasesas the size of the semiconductor chip 102 increases, which results in anincrease in the overall size of the semiconductor device. Additionally,as shown in FIGS. 23A and 23B, when the test circuit is incorporatedinto an upper semiconductor chip 104, there may be a problem in that thesemiconductor device having the test circuit cannot be stacked althoughthe semiconductor device having no test circuit can be stacked.

[0171] In order to solve the above-mentioned problems, in a thirdembodiment of the present invention, a semiconductor chip exclusive fora test is produced separately so as to be added to the semiconductorchips to be stacked.

[0172]FIG. 24 is a cross-sectional view of a stacked semiconductordevice 110 according to the third embodiment of the present invention.In the stacked semiconductor device 110, the lower semiconductor chip102 is mounted to a substrate 108 via an adhesive 112 in a face-upstate. A redistribution layer 114 is formed on the circuit formingsurface of the semiconductor chip 102. Electrodes provided on theredistribution layer 114 are connected to electrodes 108 a provided onthe substrate 108 by bonding wires 116. The upper semiconductor chip 104is secured to the redistribution layer 114 by an adhesive 118. Theelectrodes of the semiconductor chip 104 are connected to theredistribution layer 114 by bonding wires 120.

[0173] In the present embodiment, a semiconductor chip 122 having sorelya test circuit is mounted in an empty space of the redistribution layer114, and is secured by an adhesive 124. Electrodes of the semiconductorchip 122 are connected to the redistribution layer 114 by bonding wires126. That is, in order to provided the semiconductor chip 122, it ispreferable that the lower semiconductor chip 102 is sufficiently largerthan the upper semiconductor chip 104 so that an empty space is definedon the redistribution layer 114.

[0174] The lower semiconductor chip 102, the upper semiconductor chip104, the semiconductor chip 122 for testing and bonding wires 116, 120and 126 are encapsulated on the substrate 108 by encapsulation resin130.

[0175] In the above-mentioned structure, the semiconductor chip 122 fortesting is connected to both the semiconductor chips 102 and 104 so asto provide the test circuit for testing the semiconductor chips 102 and104. Accordingly, the test of the semiconductor chips 102 and 104 can beperformed by merely providing terminals for inputting test data fromoutside and for outputting a result of the test. That is, there is noneed to provide terminals 106 to the substrate 108 so as to connect theterminals of the semiconductor chips 102 and 104 to an external testcircuit. The test of the semiconductor chips 102 and 104 can be achievedby adding terminals necessary for the semiconductor chip 122.

[0176] The semiconductor chip 122 for testing can be designed after thesemiconductor chips 102 and 104 to be stacked are determined, or thesemiconductor chip 122 can be produced previously by incorporating astandardized test circuit. The semiconductor chip 122 has only the testcircuit, thereby achieving an efficient and rapid test. Additionally,the test can be simplified and the test time can be reduced.

[0177] It should be noted that although the upper semiconductor chip 104and the semiconductor chip 122 for testing are mounted to theredistribution layer provided on the lower semiconductor chip 102 in thestacked semiconductor device 110 shown in FIG. 24, the redistributionlayer 114 may be formed by the flexible printed wiring board 76 as shownin FIG. 10. The flexible printed wiring board 76 can be formed, forexample, by applying a conductive material such as a copper foil to apolyimide tape, and patterning the conductive material. When theflexible printed wiring board 76 is used, such a structure correspondsto a structure in which one of the semiconductor chips 74-1 and 74-2 inthe semiconductor device 90 shown in FIG. 13 is replaced by thesemiconductor chip 122 for testing.

[0178]FIGS. 25 through 27 show variations of the stacked semiconductordevice 110 shown in FIG. 24.

[0179]FIG. 25 is a cross-sectional view of a first variation of thesemiconductor device 110. The first embodiment shown in FIG. 25 hasbasically the same structure as the semiconductor device 110 shown inFIG. 24 except for the semiconductor chip 122 for testing being mountedto the redistribution layer 114 in a face-down state. That is, thesemiconductor chip 122 is mounted to the redistribution layer 114 byflip-chip bonding, and the upper semiconductor chip 104 is mounted tothe redistribution layer 114 in a face-up state and connected by wirebonding.

[0180]FIG. 26 is a cross-sectional view of a second variation of thesemiconductor device 110. The second embodiment shown in FIG. 26 hasbasically the same structure as the semiconductor device 110 shown inFIG. 24 except for the semiconductor chip 104 being mounted to theredistribution layer 114 in a face-down state. That is, the uppersemiconductor chip 104 is mounted to the redistribution layer 114 byflip-chip bonding, and the semiconductor chip 122 is mounted to theredistribution layer 114 in a face-up state and connected by wirebonding.

[0181]FIG. 27 is a cross-sectional view of a third variation of thesemiconductor device 110. The third variation shown in FIG. 27 hasbasically the same structure as the semiconductor device 110 shown inFIG. 24 except for the semiconductor chip 122 for testing being mountedto the redistribution layer 114 in a face-down state and thesemiconductor chip 104 being mounted to the redistribution layer 114also in a face-down state. That is, the semiconductor chip 122 ismounted to the redistribution layer 114 by flip-chip bonding, and theupper semiconductor chip 104 is mounted to the redistribution layer 114also by flip-chip bonding.

[0182] The present invention is not limited to the specificallydisclosed embodiments, and variations and modifications may be madewithout departing from the scope of the present invention.

[0183] The present application is based on Japanese priorityapplications No. 2000-267621, filed on Sep. 4, 2000, and No. 2001-121539filed on Apr. 19, 2001, the entire contents of which are herebyincorporated by reference.

What is claimed is:
 1. A stacked semiconductor device, comprising: a first substrate that has external connecting terminals; first terminals that are placed on a surface of the first substrate opposite to a surface of the first substrate on which the external connecting terminals of the first substrate are formed; at least one first semiconductor chip that is mounted on the first substrate; a second substrate that is placed on the first semiconductor chip; at least one second semiconductor chip that is mounted on the second substrate; and second terminals that are formed on the second substrate and electrically connected to at least one of the first semiconductor chip and the second semiconductor chip, the second terminals being connected to the first terminals by wire bonding.
 2. The stacked semiconductor device as claimed in claim 1, wherein: the second semiconductor chip is attached to the first terminals of the first substrate by wire bonding; the first semiconductor chip is mounted on the second substrate by flip-chip bonding; and the second terminals of the second substrate are connected to the first terminals of the first substrate by wire bonding.
 3. The stacked semiconductor device as claimed in claim 2, wherein: the second substrate has an extending portion that extends beyond an outer periphery of the second semiconductor chip; the second terminals of the second substrate are bonding pads formed at the extending portion; and the second terminals are connected to the first terminals by wire bonding.
 4. The stacked semiconductor device as claimed in claim 3, wherein: the extending portion of the second substrate has notches; and bonding wires that connect the second semiconductor chip to the first terminals of the first substrate extend through the notches.
 5. The stacked semiconductor device as claimed in claim 1, wherein: the first semiconductor chip is connected to the first terminals of the first substrate by wire bonding; the second semiconductor chip is connected to the second terminals of the second substrate by wire bonding; and the second terminals of the second substrate are connected to the first terminals of the first substrate by wire bonding.
 6. The stacked semiconductor device as claimed in claim 5, wherein: the second substrate has an extending portion that extends beyond an outer periphery of the second semiconductor chip; and the second terminals of the second substrate are connected to the first terminals of the first substrate by wire bonding via first bonding pads formed at the extending portion.
 7. The stacked semiconductor device as claimed in claim 6, wherein: the second semiconductor chip is connected by wire bonding to second bonding pads formed on the second substrate; and the second bonding pads are connected to the first bonding pads via a wiring pattern formed on the second substrate.
 8. The stacked-semiconductor device as claimed in claim 1, wherein the second substrate has an extending portion extending toward a periphery of the second substrate, and the extending portion has an end surface that is exposed in a side surface of the packaged semiconductor device.
 9. The stacked semiconductor device as claimed in claim 8, wherein the end surface of the extending portion is a cut surface formed by cutting so as to individualize the stacked semiconductor device.
 10. The stacked semiconductor device as claimed in claim 1, wherein a conductive layer is provided on a substantially entire surface of the second substrate opposite to a surface provided with the second terminals. 